Forum Discussion

AAlmo3's avatar
AAlmo3
Icon for New Contributor rankNew Contributor
7 years ago

RTL Simulation of Simple AND Gate Error?

I am using Quartus II Web Edition ver. 13. I am just starting out. I am trying to simulate the following VHDL code: -- Copyright (C) 1991-2013 Altera Corporation -- Your use of Altera Corporation's...
MuhammadAr_U_Intel's avatar
MuhammadAr_U_Intel
Icon for Contributor rankContributor
7 years ago

What you are reporting is very strange. Are you saying AND gate is giving a wrong functional behavior however resetting the simulation resolves it ?

Could you share the example archive with me to look into this and see what actually is happening. You may share in private message to me.

Thanks,

Arslan