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AAlmo3
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7 years ago

RTL Simulation of Simple AND Gate Error?

I am using Quartus II Web Edition ver. 13. I am just starting out. I am trying to simulate the following VHDL code: -- Copyright (C) 1991-2013 Altera Corporation -- Your use of Altera Corporation's...
AAlmo3's avatar
AAlmo3
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7 years ago

I've found that actually Reseting the simulation once or twice after simulating once (the button next to the simulation runtime textbox where you put how much time to run the simulation with the arrow pointing upwards) has solved the problem.