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AAlmo3's avatar
AAlmo3
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7 years ago

RTL Simulation of Simple AND Gate Error?

I am using Quartus II Web Edition ver. 13. I am just starting out. I am trying to simulate the following VHDL code: -- Copyright (C) 1991-2013 Altera Corporation -- Your use of Altera Corporation's...
MuhammadAr_U_Intel's avatar
MuhammadAr_U_Intel
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7 years ago
Hi, Indeed you r waveform looks incorrect, It seems strange for such a basic simulation results are in-correct. I tried to simulate the same code you pasted in Quartus 13.1/ Modelsim and did get correct results. Can you review your testbench setup and RTL ? Attached snapshot for reference. I used Nativelink to setup simulation as described in video. https://www.youtube.com/watch?v=PmVVXQchv2c On guidance for simulating the complete design, please refer to some useful videos/ documents listed at simulation support page. https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/quartus-support.html Let me know if you are not able to get correct results. Thanks, Arslan
AAlmo3's avatar
AAlmo3
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7 years ago

I have followed the video, which was my setup already, and have gone through the "Intel Quartus Prime Standard Edition User Guide: Third-party Simulation" part of the User Guide but I am still getting the same results. I should also add that when I download the .sof file onto my DE0 FPGA board, it does indeed show correct results.