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Honored Contributor
Honored ContributorRTL sequence to VHDL translation
How would i place this RTL sequence and convert it into VHDL input:clk,mr,x,dat[6] output:rdy,err,resa[3].resb[3] registers;rega[3]. regb[3] sequence: 0. regb<=000 1. rega <=dat [5..3...
Altera_ForumHonored Contributor
Honored ContributorHow much VHDL do you know? Try yourself first, then ask us to help on the points you are stuck on.
