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Altera_Forum's avatar
Altera_Forum
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13 years ago

ROM in VHDL

Hi All, I'm using DE2 FPGA to play something from a microphone pass it through DE2, do some filtering and play it back through de2. So far, I was successful on playing mic back from speakers. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

And another question, If I want to change my data to 32 bits, instead of 8 bits, how should change this part?

type mem_type is array (0 to 7) of std_logic_vector(7 downto 0);

signal ADC_array : mem_type :=

( 0 => "00010000",

1 => "00010001",

2 => "00010010",

3 => "00010011",

4 => "00010100",

5 => "00010101",

6 => "00010110",

7 => "00010111");

Also, if I need to read these data back to do some operation on them, can I just simply get my output I read from my memory and connect it to my other entity that I'm doing that specific operation? Or do I need to call every sample, if that make any sense. Since I have 8 samples, and I need to do this on each sample, am I gonna get one sample at a time? or all of them together? I have a very unclear view on how to deal with these output I'm reading from the array.