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Altera_Forum's avatar
Altera_Forum
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13 years ago

ROM in VHDL

Hi All, I'm using DE2 FPGA to play something from a microphone pass it through DE2, do some filtering and play it back through de2. So far, I was successful on playing mic back from speakers. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Do yo want to do the work or just infer rom(for just few samples)?

I suggest you don't worry about whether a rom is inferred or not(leave that to the tool for now).

Note your data is constant inserted by you not ADC and so contradicts what you say. 


ARCHITECTURE Behavorial OF ... IS
signal count : integer range 0 to 7 := 0;
type my_type is array (0 to 7) of std_logic_vector(7 downto 0);
constant ADC_array : my_type :=  -- { or (, not sure of syntax
  (0 => "00010000",
1 => "00010001",
2 => "00010010",
3 => "00010011",
4 => "00010100",
5 => "00010101",
6 => "00010110",
7 => "00010111");
begin
process(clk)
begin
if (rising_edge(clk)) then
   if (adc_full = '1') then
      count <= count + 1;
   end if;
   data <= ADC_array(count);
end if;
end process;
end architecture;