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Altera_Forum
Honored Contributor
Honored ContributorROM and RAM connection
Hello, Im trying to connect ROM with RAM blocks,for this Im write top level entity and connected output of ROM with RAM This is code for ROM LIBRARY ieee; USE ieee.std_logic_1164.all;
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Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- how is it looks now? --- Quote End --- code ok but overall idea unclear. What do you put in rom (with dual port output). You then address rom from outside and address ram from outside. What is the purpose. I also suggest (strongly) changing the name cloc to clock or clk just for consistency. check your rom code address range(now 0~255).
