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Altera_Forum
Honored Contributor
Honored ContributorROM and RAM connection
Hello, Im trying to connect ROM with RAM blocks,for this Im write top level entity and connected output of ROM with RAM This is code for ROM LIBRARY ieee; USE ieee.std_logic_1164.all;
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Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- ok,so as I understood,I made only conversion and no logic involved in FPGA,so i didnt connect those data_.... ports? --- Quote End --- you wired them but after conversion so that signal types match and tool does not reject it.
