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Altera_Forum
Honored Contributor
Honored ContributorROM and RAM connection
Hello, Im trying to connect ROM with RAM blocks,for this Im write top level entity and connected output of ROM with RAM This is code for ROM LIBRARY ieee; USE ieee.std_logic_1164.all;
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Altera_ForumHonored Contributor
Honored Contributoryes,now its working,but i dont see connection between data_a_i and data_a, data_b_q and data_b)sorry my bad.yes i need just 8.but what about,data_a and data_a_i should be connected,so this mean that those signals should be internal,and we dont need to declare it in TOP level entity.Am I right?
