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Honored Contributor
Honored ContributorRidiculous interconnect timing between related clocks
I'm trying to finalize a design in an Arria 10, using Quartus Prime Pro 16.1 , where a signal is passed from a global clock to a related peripheral clock of the same frequency (they are both derived ...
Altera_ForumHonored Contributor
Honored Contributor@Tricky. Happy Holidays!, could you please share how exactly one would "relax hold time on the fanout of this register".
