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Altera_Forum's avatar
Altera_Forum
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8 years ago

Ridiculous interconnect timing between related clocks

I'm trying to finalize a design in an Arria 10, using Quartus Prime Pro 16.1 , where a signal is passed from a global clock to a related peripheral clock of the same frequency (they are both derived ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Good call on checking what the routing was trying to do - turns out it actually was routing the signal half way round the device in an attempt to make a hold requirement that is utterly nuts! I'm working on playing with multicycle constraints to get it to actually analyze the path in a more sane way...

Thanks all for the help!