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Altera_Forum's avatar
Altera_Forum
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8 years ago

Ridiculous interconnect timing between related clocks

I'm trying to finalize a design in an Arria 10, using Quartus Prime Pro 16.1 , where a signal is passed from a global clock to a related peripheral clock of the same frequency (they are both derived ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Yes, I have seen long timing paths due to routing delays in A10 designs. Check for congestion in the chip-planner. Also locate failing path and select highlight routing. If it takes multi-segment routes you may have an issue of available routing resources. Post a picture of your routing wire utilization. Good luck!