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Daniel99's avatar
Daniel99
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8 months ago

Restricted Fmax due to minimum period

I have created a simple project with a 500 MHz clock fed into a clock pin set for LVDS. This clock goes only to a divide-by-4 block (two flip-flops) and the resulting 125 MHz is fed to an output pin....
Timing
Daniel99's avatar
Daniel99
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8 months ago

Thank you again.

But I can't help feel some contradiction regarding your last paragraph.
Since there is no way I can tell Quartus about which differential voltage swing I will apply to an LVDS input pin (or is there?), it will, in my case, give me the restricted Fmax based on table 20 and not from table 19.
So when you say that "whether your implementation can actually achieve [frequencies above 500 Mbps] depends on the routing quality, board-level signal integrity, and internal FPGA timing, all of which Quartus can evaluate directly", does it mean that I can ignore the restricted Fmax after all, and safely apply my 500 MHz clock, with a good voltage swing, to an LVDS input and use my design as is, since the Fmax reported is something like 900 MHz?

Sorry for this long thread...