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I notice you're using the sclk to clock the logic - the usual way of working is to use a system clock (clk in your case) that is many times the frequency of sclk, and treat sclk as any other signal and sample it. Then you generate "rise" or "fall" pulses to enable the registers in your design that all run at the system clock frequency.
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Yeah that was my first implementation:
http://pastebin.com/r7y7u7tx But I have 1% of error with this implementation.
My main clock(25MHz) is not much faster than SCLK(4MHz if possible I want to work at 10MHz) maybe that is why I can not have the implementation based on main clock.
But still I can not understand why the implementation based on SCLK do not work at all any ideas?
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