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Altera_Forum
Honored Contributor
Honored ContributorRequest of feedback on SPI Slave moduel
Hello I'm new on the hardware design world so probably I'm making a some beginner mistake. I need to write a SPI Slave module, my first attempt was to make a SPI slave module using as refe...
Altera_ForumHonored Contributor
Honored ContributorI notice you're using the sclk to clock the logic - the usual way of working is to use a system clock (clk in your case) that is many times the frequency of sclk, and treat sclk as any other signal and sample it. Then you generate "rise" or "fall" pulses to enable the registers in your design that all run at the system clock frequency.
