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Altera_Forum
Honored Contributor
8 years agoI'm not sure if this is allowed but I have a problem with simulation.
https://www.alteraforum.com/forum/attachment.php?attachmentid=13657 The overall output of the entire program works but I want to see the internals. I get Us when I run a simulation for example I'm expecting the same output for "step" as "ROM:U1|address" U1 is a 1-port RAM that I instantiated and implemented as "ROM".