Forum Discussion
MTett
New Contributor
New ContributorRelative paths in SystemVerilog
I want to include a text file I want to read and write to. However, verilog is unable to find the text in the current directory. How do I determine relative path in System Verilog. I have tried the ...
KennyT_altera
Super Contributor
Super ContributorIt should work, can you attached your design.qar here to have a look? file = $fopen("data.txt", "r");
MTettNew Contributor
New ContributorMy bad. So basically I am using a tool(connects to modelsim) which automates the simulation of this design module against a testbench. So it works with the individual files as opposed to the project file. This could be the problem.
