Registers in I/O cells

If I remember correctly, there is no input register in the IO cell, but a direct connection from the IO cell to the LAB, which is almost as fast. On the output side there should be a 2 registers, because doing DDIO interfaces in the LAB is far too slow(the mux after the registers becomes a LUT to route through and it gets ugly)

Hmm.

• The two output registers and two OE registers are used for DDR applications

• You can use the input registers for fast setup times and output registers for fast clock-to-output times

• You can use the OE registers for fast clock-to-output enable times

It all depends on your timing constraints and if you are using the "Fast I/O register" assignments. Using the registers in the I/O is not always good (and not regularly done by the Fitter) because it's possible to fail hold timing on the I/O to the upstream or downstream device. If you want to force the use of the I/O registers, use a Fast Input or Fast Output register assignment in the Assignment Editor.

Thanks. Enabling "fast input register" for one of my buses certainly got usage of the corresponding number "i/o registers" in the fitter summary, though it's not clear from the netlist viewers whether I had actually got what I had in mind.

    component altera_gpio_lite is
        generic (
            PIN_TYPE                                 : string  := "output";
            SIZE                                     : integer := 4;
            REGISTER_MODE                            : string  := "bypass";
            BUFFER_TYPE                              : string  := "single-ended"
;
            ASYNC_MODE                               : string  := "none";
            SYNC_MODE                                : string  := "none";
            BUS_HOLD                                 : string  := "false";
            OPEN_DRAIN_OUTPUT                        : string  := "false";
            ENABLE_OE_PORT                           : string  := "false";
            ENABLE_NSLEEP_PORT                       : string  := "false";
            ENABLE_CLOCK_ENA_PORT                    : string  := "false";
            SET_REGISTER_OUTPUTS_HIGH                : string  := "false";
            INVERT_OUTPUT                            : string  := "false";
            INVERT_INPUT_CLOCK                       : string  := "false";
            USE_ONE_REG_TO_DRIVE_OE                  : string  := "false";
            USE_DDIO_REG_TO_DRIVE_OE                 : string  := "false";
            USE_ADVANCED_DDR_FEATURES                : string  := "false";
            USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY : string  := "false";
            ENABLE_OE_HALF_CYCLE_DELAY               : string  := "true";
            INVERT_CLKDIV_INPUT_CLOCK                : string  := "false";
            ENABLE_PHASE_INVERT_CTRL_PORT            : string  := "false";
            ENABLE_HR_CLOCK                          : string  := "false";
            INVERT_OUTPUT_CLOCK                      : string  := "false";
            INVERT_OE_INCLOCK                        : string  := "false";
            ENABLE_PHASE_DETECTOR_FOR_CK             : string  := "false"
        );
    port (
      inclock         : in    std_logic                    := 'X';              
      dout            : out   std_logic_vector(7 downto 0);                     
      pad_in          : in    std_logic_vector(7 downto 0) := (others => 'X');  
      inclocken       : in    std_logic                    := 'X';              
      fr_clock        : out   std_logic_vector(7 downto 0);                     
      hr_clock        : out   std_logic;                                        
      invert_hr_clock : in    std_logic                    := 'X';              
      outclock        : in    std_logic                    := 'X';              
      outclocken      : in    std_logic                    := 'X';              
      phy_mem_clock   : in    std_logic                    := 'X';              
      mimic_clock     : out   std_logic_vector(7 downto 0);                     
      din             : in    std_logic_vector(7 downto 0) := (others => 'X');  
      pad_io          : inout std_logic_vector(7 downto 0) := (others => 'X');  
      pad_io_b        : inout std_logic_vector(7 downto 0) := (others => 'X');  
      pad_in_b        : in    std_logic_vector(7 downto 0) := (others => 'X');  
      pad_out         : out   std_logic_vector(7 downto 0);                     
      pad_out_b       : out   std_logic_vector(7 downto 0);                     
      aset            : in    std_logic                    := 'X';              
      aclr            : in    std_logic                    := 'X';              
      sclr            : in    std_logic                    := 'X';              
      nsleep          : in    std_logic_vector(7 downto 0) := (others => 'X');  
      oe              : in    std_logic_vector(7 downto 0) := (others => 'X')   
    );
  end component altera_gpio_lite;