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Altera_Forum's avatar
Altera_Forum
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15 years ago

Register count / logic utilization blows up in 10.1.sp1?

Is there some reason Quartus v10.1.sp1 is generating a LOT more dedicated logic registers than Quartus v9.1.sp1?

If so, is there a switch/option or .ini variable I can set to fix this?

I have an EP3LS150 that's reporting about 80% logic utilization and 80K dedicated logic registers when compiled in Quartus v9.1.sp1

I recompiled in v10.1.sp1 and the device would not fit, as it tried to use over 113K dedicated logic registers!

I've deleted the db/ and incremental_db/ directories and tried again.

Regenerated FFT IP in v10.1.sp1 and tried again.

Regenerated/reimported my .qxp in 10.1.sp1 and tried again.

Turned off auto_logic_duplication and auto_register_duplication and tried again.

Everything combined got me down to about 100K registers and 98% utilization.

Thanks for your help.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    It would be interesting to know, if the difference can be related to a particular design entity when comparing the resource utilization tables.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Most likely something that was going into memory(either a large shift-register or a memory) is now going into FFs. Without that, the number of registers should be very close.

    I open both projects in Quartus at the same time. The Project Navigator in the top-left allows you to dive down into each hierarchy. It also shows statistics on each hierarchy, such as M9Ks, DSP blocks, ALUTs, ALMs, and of course, Dedicated Logic Registers. With the two side by side, just dive down into sub-hierarchies and look for large differences. Most likely you'll find one hierarchy that accounts for all the differences. Then look at memory counts and see if they're different.

    If the register difference is "spread throughout", then most likely something got synthesized out in 9.1 that allowed for reductions throughout the design, and it's not occuring in 10.1. That will be more difficult, but is the less likely culprit.

    Also, I would try to use the same code, i.e. the same version of the FFT IP. If you're reading in different libraries, that also could be the problem. (Although diving into the hierarchies as explained would help identify this.)