Altera_ForumHonored Contributor9 years agoreg [ x +: 12] mean ? what is the meaning of this syntax? here x could be input vector reg [ x +: 12] please help !!
Recent DiscussionsSSLC Login Issue – "You need to enroll" loop after OTP verificationflexlm errorQuesta Sim on Windows - linking to external LIBSolvedFree Licence for Max+PlusIIQuartus crashes on long carry chain in Agilex 5 FPGAs