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PFour2
New Contributor
New ContributorReference Clock/InClock for the LVDS SERDES I/OPLL in the Arria 10 on Quartus 18.1
Hello, I am working on Quartus Pro 18.1 with an Arria 10. In the design I need to use, as a tranceiver, a LVDS SERDES IP for 18 channels in the Bank 3A. The problem I have is in regard of the Refe...
SreekumarR_G_Intel
Frequent Contributor
Frequent ContributorHello ,
Sorry , I didnt notice your reply ..
Answer to your question,, Yes It is to reduce the jitter error , Quartus tool is intelligent enough to calculate take the preventive measure during fitter.
About the external PLL , yes you are correct .It will instantiate the same PLL as one it creates internally.but only difference is you can constraint the PLL in qsf based on your design.
Kindly let me know if you have any questions /concern ?
Thank you ,
Regards,
Sree
