New Contributor
New ContributorHello,
Sorry for the delay !
To answer AndyN question it is an off-the-shelf solution that I am designing.
The problem that I have is that a PCB has already been done for the pins with the dedicated clock pins of the Bank3A as outputs of the LVDS SERDES (thinking that it was possible to use any clock of the board as the reference clock for the PLL feeding the LVDS SERDES). I wanted to be sure that it is required to modify the PCB.
I have tried, with different clock linked to the reference clock of my PLL, to set the assignment as you said. However I keep having the same Fitter error regardless of the assignment:
"The reference clock on PLL "..|..|internal_pll.pll_inst|altera_lvds_core20_iopll", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification."
By using the reference clock pin I have completed the compilation, so it seems that it is mandatory to do so but I didn't find in the documentation where it is mentionned that it is. Because for the I/O PLL the documentation specifies that the reference clock could be GCLK or RCLK for instance, but it seems that if it used for the LVDS SERDES only the dedicated clock pins are accepted ? And so, why this constrain ? To avoid a terrible jitter as you said ?
Also, it is possible to use an external PLL to feed the LVDS SERDES. But for me it is basically the same PLL as the one it creates internally with the LVDS SERDES IP. Do you have any clarification on what the external PLL is or what it means ?
Thank you in advance for your answer.
Best regards,
Pierre.
