Reference Clock/InClock for the LVDS SERDES I/OPLL in the Arria 10 on Quartus 18.1

I agree with Andrew. I believe you should use the corresponding bank Ref clock pin for IOPLL. Also your question output of the PLL is connect to another input of PLL.I believe when you do this you will get fitter error. set the below assignment but dont use PLL(i know it is bad choice) if it is working you can atleast test the functionality Here is the quartus prime setting assignment , set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to <name of toplevel reference clock input port> kindly let me know how it go ? thank you , Regards, Sree