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Altera_Forum's avatar
Altera_Forum
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15 years ago

Reducing SlewRate on FLEX10KE device IO

We have recently developed a device using a FLEX10KE, and we are having difficulties reaching our EMC targets.

The device is such that it cannot be shielded further through metalisation of the casing or such. Before we try relaying out the PCB i was interested if there are any options with the FLEX to reduce slew rate.

We have turned on slow slew rate, however this has little effect as it is only modifying the slew rate of the falling edge.

Apparently it is possible to current limit the output of the pins using the Assignment Editor, (I've Checked Logic Options => I/O Features, and also browsed through all categories) however i am unable to locate this feature.

Does anyone have a suggestion or know how to setup the current limiting?

We are running Quartus II Version 9, Service Pack 2 as this seems to be the last version of Quartus to support the FLEX architecture.

Thanks

Ryan

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    There's a simple answer. Consult the flex10ke device handbook. Do you see other programmable IO features than Slow Slew Rate, PCI Clamp and Open Drain? No. That's it, unfortunately.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thankyou for your prompt reply, i guess its back to pcb layout then.

    I know some of the FPGA's are capable of current limiting the output, i was just hoping that they were using an unfamiliar terminology that i missed.

    Regards

    Ryan