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Honored Contributor
Honored ContributorReducing Interconnect (IC) delay with evenly distributed pipeline stages
Hi, I am getting setup violations because of large interconnect delay. I've added several pipeline stages to reduce the interconnect delay but Quartus is not doing a very good job of spreadin...
Altera_ForumHonored Contributor
Honored ContributorWow, you're definitely stretching the clock frequency limits, Philippe. In fact I think you've blown through them. But it sounds like you've got it working. Nice work!
Bob
