Reducing Interconnect (IC) delay with evenly distributed pipeline stages

Well I feel a bit silly. I just removed all location assignments as a test and Quartus was able to meet all timings better than any previous compilation. I've tried so many different things in the last 2 days that it's hard to remember all my steps but here's the general idea:

1) I started out with a poor design that could not meet timing (dozens of failing paths).

2) I made timing optimizations to the code (duplicating logic so that each IO cell had its own serialization logic) and I added location constraints on key registers. Timing greatly improved but a handful of paths still failed. About 6 out of 180 of the registers that I had manually placed still had large interconnect delay even though the source and destination were right next to each other (ex. FF_X49_Y1_N1 --> FF_X49_Y1_N22 with 1.1 ns IC delay)! It's as if the signal was taking a long detour (maybe I had placed the register in a congested area?) and my location constraint was doing more harm than good.

3) I removed all location constraints and timing passed.

It seems like writing better code is much more effective at improving timing than trying to beat Quartus at placing logic. I'm left wondering if register location constraints are ever a good idea.