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Thanks for the replies.
Tricky:
I am fanning out a single source register to several output registers in IO cells across the FPGA with register stages in between with the hopes of reducing interconnect delay. The source register is somewhere in the middle of the IO cells. I'm not sure how to define a region to improve timing in this scenario. My initial thought was to manually place each register with location assignments of the type:
set_location_assignment FF_X46_Y1_N1 -to pipeline[1]
Kaz:
There is no combinational logic between the register stages. I just have a chain of registers going from point A to point B where the distance between A and B is about half the FPGA. If I try to cover that distance in 1 hop (A->B) then TimeQuest reports setup violations and I can see that the culprit is huge interconnect (IC) delay. So I add register stages between A and B to create smaller hops (less IC delay between each stage). The problem is that Quartus clusters the extra registers between A and B so there is still a hop that is large enough to cause a setup violation.
Update: I've resorted to manual location assignments to limit the distance between each register stage. It works.
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Philippe -
That's unfortunate you had to lock things down. That makes for an inflexible design if things change in the future.
I'm curious if your problem even makes sense. What device and speed grade are you targeting and what is the frequency of "clk"? Also, what is the fanout from source to destination? And what version of Quartus are you running?
Bob
Honored Contributor
