--- Quote Start ---
Thanks for the replies.
Tricky:
I am fanning out a single source register to several output registers in IO cells across the FPGA with register stages in between with the hopes of reducing interconnect delay. The source register is somewhere in the middle of the IO cells. I'm not sure how to define a region to improve timing in this scenario. My initial thought was to manually place each register with location assignments of the type:
set_location_assignment FF_X46_Y1_N1 -to pipeline[1]
Kaz:
There is no combinational logic between the register stages. I just have a chain of registers going from point A to point B where the distance between A and B is about half the FPGA. If I try to cover that distance in 1 hop (A->B) then TimeQuest reports setup violations and I can see that the culprit is huge interconnect (IC) delay. So I add register stages between A and B to create smaller hops (less IC delay between each stage). The problem is that Quartus clusters the extra registers between A and B so there is still a hop that is large enough to cause a setup violation.
Update: I've resorted to manual location assignments to limit the distance between each register stage. It works.
--- Quote End ---
Normally quartus should not put unduely long delays between registers unless there is too many layers of comb. logic.
I am not sure I understand why quartus puts such delay from A to B in your case. Moreover if you have freedom to put extra pipe registers then it means you don't worry about the rule of one clock of timing(default multicycle) and so your solution of extra pipe registers is equivalent to adding multicycle and then save some registers.
In short, you can just add multicycle, or set max delay or add pipe that quartus spreads along path or force manual fitting.
Honored Contributor
