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Honored ContributorReducing Interconnect (IC) delay with evenly distributed pipeline stages
Hi, I am getting setup violations because of large interconnect delay. I've added several pipeline stages to reduce the interconnect delay but Quartus is not doing a very good job of spreadin...
Altera_ForumHonored Contributor
Honored Contributoradding registers back to back does not help reduce delay. You need to break down comb. logic cloud into smaller chunks using register
