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Altera_Forum
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9 years ago

Reducing Interconnect (IC) delay with evenly distributed pipeline stages

Hi, I am getting setup violations because of large interconnect delay. I've added several pipeline stages to reduce the interconnect delay but Quartus is not doing a very good job of spreadin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Have you thought about creating regions? This way you can assign things (whole entities down to individual registers) to be placed into the region, and they will usually get priority over other logic.