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Altera_Forum
Honored Contributor
Honored ContributorReducing Interconnect (IC) delay with evenly distributed pipeline stages
Hi, I am getting setup violations because of large interconnect delay. I've added several pipeline stages to reduce the interconnect delay but Quartus is not doing a very good job of spreadin...
Altera_ForumHonored Contributor
Honored ContributorHave you thought about creating regions? This way you can assign things (whole entities down to individual registers) to be placed into the region, and they will usually get priority over other logic.
