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Altera_Forum
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15 years ago

recovery issue

Hi all! I use an Altera DCFIFO with the option "resynchronize aclr in wr_clk domain". Until today, aclr port of my DCFIFO was directly connected to a pin of my device. Today, I change...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You're right. Until you put a set_input_delay constraint on the I/O, TimeQuest doesn't know how to time the circuit, so you wouldn't get any timing failures. It would show up under Unconstrained Paths though