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Why didn't I get these errors when aclr was connected to a pin of the device?
Because we have no warranty of any kind about the timing of signals from this pin, so...
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The Quartus II compiler just assumes that you know what you are doing if you connect a physical FPGA pin directly to a function. Unless you tell Quartus that it is asynchronous (by setting a false path) it assumes that is well behaved and respects the actual Tsu and Th requirements as posted in the Datasheet Report section in TimeQuest.
BTW you can also set a false path for the input pin only e.g.
set_false_path -from Reset_pin -to *
so you don't have to look up all those names. And imho is better and more appropiate. TimeQuest (and the Fitter) will properly constrain the 2-register anti-metastability chain.
Honored Contributor
