Recovery - DCFIFO issue

Since one clk is slow and one is fast then there is a simple trick to synchronise reset on both clks as follows:

Process
begin
wait until fast_clk = '1';
 
   reset_1d <= reset;
   reset_2d <= reset_1d;
 
   slow_clk_1d <= slow_clk;
   slow_clk_2d <= slow_clk_1d;
   slow_clk_3d <= slow_clk_2d;
 
   if slow_clk_2d = '0' and slow_clk_3d = '1' then
       reset_3d <= reset_2d;
   end if;
 
end process;

As such reset_3d is synchronised to edge of fast clk and occurs shortly after falling edge of slow clk. so violation on slow clk is impossible since reset transition is well ahead of next slow edge.

Note that reset doesn't trigger the slow flips so no double stage registers needed on slow clk.