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I'm not a proponent of overclocking. PCs give me enough headaches with stable hardware....
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Ok, here is the poor mans way to shorten compile time:
1. Use Q2 9.1sp2, or, Q11 32 bit. (Q10 64 bit is slower)
2. Run your prototype project at a lower frequency & higher speed grade & gate count FPGA with these settings in Q2:
Physical Synthesis Optimizations -> all off (affects the fitter compile time)
Analysis & Synthesis Settings -> disable Timing Driven Synthesis.
More Analysis & Synthesis Settings / Synthesis Effort -> Fast (affects analysis & synthesis time, If your project uses a huge number of logic cells as memory arrays and your Fmax is really bad, keep this in auto)
Fitter Settings / Fast fit. Fitter Settings / placement effort & Router effort -> 0.25
Fitter Settings / Router timing optimization level -> Minimum
Fitter Settings / SSN optimizations -> off
If you are using logic cells as memory arrays, this also slows down compilation by a considerable amount.
Note on my current project, filling 50% of an EP3C55, I went from 10 minutes to 7 minutes with these settings. After overclocking only my PC's ram modules & disabling Windows's virtual file, the 7 minutes went down to 4 minutes.
Also note that overclocking your CPU or bus speed has very little effect.