Read/Write Access in Nios II

It's my bad, I wasn't very clear when I mentionned random timing.

What I meant is that I observed these transactions at very random time, for a GIVEN simulation run.

When I run several simulation sets in a row, these acceses do happen always at the same time from one run to another, which is rather logical.

I want to understand the mechanisms that are at stake when I run my code on the Nios II.

For argument's sake here the code of the functions AHW_Read_Access and AHW_Write_Access:

EXTERN en_ret_code AHW_Read_access(
st_AHW_ahw *p_ahw, /* Structure de registres sur laquelle appliquer la fonction */
u_int_32 address_MCU,
u_int_32 addr_offset
)
{
en_ret_code ret = RET_CODE_OK;
 
 
u_int_32* ptr; 
 
//ptr recupere l'addresse MCU + offset
ptr = (u_int_32 *)(address_MCU + addr_offset);
 
//dereferencement
p_ahw->reg0 = *ptr;
printf("Addresse Ecriture Bus Local : %x Valeur : %x \n", address_MCU,p_ahw->reg0);
 
return(ret);
}
 
 
EXTERN en_ret_code AHW_Write_access(
st_AHW_ahw *p_ahw, /* Structure de registres sur laquelle appliquer la fonction */
u_int_32 address_MCU,
u_int_32 addr_offset,
u_int_32 data_to_be_written
)
{
en_ret_code ret = RET_CODE_OK;
 
 
u_int_32* ptr; 
 
//ptr recupere l'addresse MCU + offset
ptr = (u_int_32 *)(address_MCU + addr_offset);
 
//dereferencement
*ptr = data_to_be_written;
 
//printf("Addresse Ecriture Bus Local : %x Valeur : %x \n", address_MCU,*ptr);
return(ret);
}

u_int_XX (8, 16, 32, 64) are just typedefs for unsigned char, signed char, unsigned short etc..