Forum Discussion
mahender
New Contributor
5 years agosymbol creation in quartus prime pro.
How to create symbol for verilog file in quartus prime pro and simulate it.
I am very new to this,please answer me.
Thanks in advance...!
mahender
New Contributor
5 years agoHi @SyafieqS ,
That video is so helpful and that i have used for ip simulation,but i am asking for block design.I have created block design using one or more ip's(interconnection),simulation can be done as per your previous answer but what i have to do to instantiate the block diagram in testbench(for ip after simulation instance code will be generated and that code i use in the testbench)..?how can i generate instace file for block design..i have block design file like this...