Forum Discussion
mahender
New Contributor
5 years agosymbol creation in quartus prime pro.
How to create symbol for verilog file in quartus prime pro and simulate it.
I am very new to this,please answer me.
Thanks in advance...!
mahender
New Contributor
5 years agoHi @SyafieqS,
By using this pdf only i can able to create my own ip,and able to create block design.But how to simulate this block design using testbench like we do in xilinx by creating and instantiating the wrapper file in testbench.
Thanks in advance....!
- SyafieqS5 years ago
Super Contributor
You can do that, might need to watch below tutorial on how to do the simulation
https://www.youtube.com/watch?v=eviC0jP90ZA
Also might need to look into below document for details if you re using other tools
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-tp-simulation.pdf