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Junmo's avatar
Junmo
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3 years ago

Modelsim Simulator Error & Request about solutions and source files

I have a two questions. First, I use the quartus 18.1 version and run gate level simulation using VWF. I can see the simulation waveform result but in this waveform the delay isn't considered....
hareesh's avatar
hareesh
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3 years ago

Hi

Did you tried in Modelsim?

Junmo's avatar
Junmo
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3 years ago

Yes.

I runned the Gate level simulaion on Quartus II 18.1 version using VWF university program.

  • hareesh's avatar
    hareesh
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    3 years ago

    Hi @Junmo ,

    I think in your design you are not using CLK. for reference i am sharing full adder VHDL code(i am not good in Verilog HDL, so i sharing VHDL) and simulation output files. Go through bellow attached files.

    Thanks,