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Junmo's avatar
Junmo
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4 years ago

Modelsim Simulator Error & Request about solutions and source files

I have a two questions. First, I use the quartus 18.1 version and run gate level simulation using VWF. I can see the simulation waveform result but in this waveform the delay isn't considered....
hareesh's avatar
hareesh
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4 years ago

Hi

I sharing customer support for ASAP issue. pls contact there.

if you don't have any another quire i'll close the case. pls conform me.

https://it.intel.com/#/topic/5457

Thanks,

Junmo's avatar
Junmo
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4 years ago

I can't access that link. Is that right?

Would you mind checking that link?

And, I got the solutions today morning. But I couldn't solve 0ns delay on Gate level simulation in VWF.

Thanks.

  • hareesh's avatar
    hareesh
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    4 years ago

    Hi

    Did you tried in Modelsim?

    • Junmo's avatar
      Junmo
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      4 years ago

      Yes.

      I runned the Gate level simulaion on Quartus II 18.1 version using VWF university program.

      • hareesh's avatar
        hareesh
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        4 years ago

        Hi @Junmo ,

        I think in your design you are not using CLK. for reference i am sharing full adder VHDL code(i am not good in Verilog HDL, so i sharing VHDL) and simulation output files. Go through bellow attached files.

        Thanks,