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bteddy's avatar
bteddy
Icon for New Contributor rankNew Contributor
3 years ago

Getting errors when I run analysis and elaboration.

Hello, I have a verilog file "10ustep_stepperdriver.v" attached. Using Quartus II 64-bit ver.13.1 web edition. I was trying to run analysis and elaboration to get a RTL netlist (schematic). I...
bteddy's avatar
bteddy
Icon for New Contributor rankNew Contributor
3 years ago

thanks for the reply.

Not my code.

Came from another board, can't find author.

So, I should named the top-level entity in project 10ustep, and the module name should be the same "10ustep"?

How do I get it to create the schematic so I can do the wires?

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Yes, the top-level entity name must match. Just select "Set as top-level entity" from the Project menu with this file open in Quartus.

    As for your second question, I'm not talking about a schematic. This is Verilog code and you need "wire" signal declarations for all named signals in the design like you have for QA, QB, QC, and QD.