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MasterBlaster's avatar
MasterBlaster
Icon for New Contributor rankNew Contributor
8 days ago
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Clock Domains and Clock Domain Crossing (CDC)

The FPGA design uses two clock domains: 100 MHz and 40 MHz. Clock domain crossing (CDC) between these domains is handled as follows: Data transfer (100 MHz → 40 MHz): A FIFO is used to provide rel...
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  • sstrell's avatar
    sstrell
    8 days ago

    The whole point here is to guide the Fitter after cutting timing between the two clock domains, so the answer to your first question is yes.  The two domains are cut from each other and then set_max_skew and set_data_delay are used to define skew between bus paths between the clock domains and the data path delay between the endpoints of the two sides of the cut paths.

    As for the values to use, just use the recommended values you show in that slide.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
8 days ago

The whole point here is to guide the Fitter after cutting timing between the two clock domains, so the answer to your first question is yes.  The two domains are cut from each other and then set_max_skew and set_data_delay are used to define skew between bus paths between the clock domains and the data path delay between the endpoints of the two sides of the cut paths.

As for the values to use, just use the recommended values you show in that slide.