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pnp's avatar
pnp
Icon for New Contributor rankNew Contributor
4 years ago
Solved

Bus index reversal when SystemVerilog module instantiates a BDF in Quartus Prime Pro 21.2

I have a legacy BDF that I need to use in a current design. Using Quartus Prime Pro v20.4 or v21.2, I see the bus indexes reversed on the port connections when the BDF diagram is instantiated from wi...
  • sstrell's avatar
    sstrell
    4 years ago

    Yeah, I'd just convert to HDL and use that if you have more complex designs causing this issue. Just save yourself the time and effort trying to fix the schematics.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

Yeah, I'd just convert to HDL and use that if you have more complex designs causing this issue. Just save yourself the time and effort trying to fix the schematics.

pnp's avatar
pnp
Icon for New Contributor rankNew Contributor
4 years ago

Thanks. We opted to create a Verilog wrapper that bit-reverses all inputs and outputs to the schematic module, which should get us by for now.

I appreciate all of your help. It would be great if Intel would acknowledge this is a bug in the software and maybe even fix it...

Regards,

Paul