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remov_b4_flight's avatar
remov_b4_flight
Icon for New Contributor rankNew Contributor
4 months ago

'*.vho not found' in Modelsim ALTERA

Dear sirs, At QuartusII 13.1 / Stratix3 project, "DDR3 SDRAM Controller with UniPHY" IP on our design. I finished synthesys and run modelsim 10.1d for RTL simulation, After launched modelsim and ...
Simulation
remov_b4_flight's avatar
remov_b4_flight
Icon for New Contributor rankNew Contributor
4 months ago

Hi,

I ran EDA Netlist writer but only generated top level module vho file

not IP module .vho file.

Is there option to do this?

AlanCLTan's avatar
AlanCLTan
Icon for Occasional Contributor rankOccasional Contributor
4 months ago

Hi,

Please ensure IP Generation is complete. Make sure the IP core has been fully generated using the IP Catalog. This process should create the necessary simulation files.

1. Use the EDA Netlist Writer
Quartus uses the EDA Netlist Writer to generate simulation files like .vho (VHDL Output). For configuration steps:

  • Go to Assignments > Settings > EDA Tool Settings > Simulation.
  • Choose ModelSim-Altera as the tool.
  • Set the Format to VHDL.
  • Under Output, ensure Generate simulation netlist is checked.

2. After setting up the simulation tool:

Go to Tools > Run EDA Simulation Tool > RTL Simulation or manually run the EDA Netlist Writer via:

quartus_eda --simulation <project_name>

This typically generates the .vho file for the top-level design. However, if you need the .vho for the IP module itself, you may need to:

Open the IP folder (usually under ip/<ip_name>/simulation/). Look for .vho or regenerate using the IP generation tool with simulation files enabled.

Best regards,

Alan Tan