New ContributorHello, I am looking to connect a Raspberry Pi 4b to an DE10 Lite Fpga. We are sending a 16bit signed little endian data stream through SPI to the FPGA, where it will be processed through an LMS filter, and sent back to the Pi. I have the code for the filters from other sources, but I am not super familiar with Verilog syntax, and am looking for some guidance on what code structure I will need to achieve this.
Regular ContributorHi,
Perhaps this could help you: https://www.thinkmind.org/articles/cenics_2019_1_20_50029.pdf
Let me know if you have further questions.
Regards,
Nurina
Regular ContributorHi,
We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
Regards,
Nurina
P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!
