Altera_Forum
Honored Contributor
16 years agoRAMs synthesized away?
Hi,
I'm designing a system that reads data, store them in block RAM, and reads them from block RAM to feed some other design. However, when I was trying to synthesize the system, some of block RAMs (yeah, some of, not all) are synthesized away! To be exact, let me describe this way: I have to load data to mem_parm1, mem_parm2, mem_x, mem_y, all of which are block rams. and they are read by a design called calc. After synthesize, mem_parm1 and mem_parm2 disappeared, only mem_x and mem_y are left. The whole system passed functional simulation in Modelsim AE 6.4 starter version. Any suggestion on this? Thanks!