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I had to convert it to a std_logic_vector in the function so the last generic would accept it, and convert it back to the memory format in the memory .vhd file, so I wouldn't have define the mem_t type in the package and pass it on to the entity, keep in mind the mem_t type is different depending of the other generic settings.
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I think that was the right decision. Sometimes there are several solutions to a problem, and going with the least-code is often the easiest way to go, and it makes it easier for the next person to read your code. Everyone knows what a big std_logic_vector is, and its more work to look up a package and see what the definition of the 2D array is.
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The single entity generates the 131072 bits (55% of my FPGA, can't make more). I have tested it in a higher level entity making 4 different sized and I have some strange errors reaching 16384 bits on one of them so I have some homework. I also have to make sure it can run as a symbol on the block_diagram/schematic.
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Give up on schematic diagrams, they are not a good idea. You will be making life difficult for the person writing the testbench for your design. Code everything in HDL.
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Thank you for the good information, now I know it's possible.
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If you want to see an example of VHDL generics and functions used in crazy ways, go and read my LFSR/PRBS tutorial and its associated source code;
https://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf https://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip Its cool that you can use VHDL pre-processing of functions to create matrices and static vectors that then get efficiently turned into logic.
Cheers,
Dave
Honored Contributor
