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My requirement is to have only one single .vhd file defining the entity/architecture, and here is the reason
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Sure, that is no problem. Lets say I have generics AWIDTH and DWIDTH. Then the hex file will have 2**AWIDTH x DWIDTH entries. Each instance of your component will be different, but the HDL identical.
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The generics work fine, however the data requires a function to generate information.
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Ok, that is fine, you could have the function in a package and pass it the same generics as the component, or just have the initialization data as another port, eg.,
u1: controller
generic map (
TYPE => "SPI",
AWIDTH => 12,
DWIDTH => 32,
INIT => mem_contents("SPI",12,32)
);
port map (
...
If you want me to take your current attempt and modify it, post some code.
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the single .vhd entity/architecture file should be the one placed in the next project, and the generics and/or data function could be created separate
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No, that is not how you should do it :)
Your code should live in a versioned repository and all projects should refer to the *single* copy of the source code. The generics would be controlled by either the project specific HDL via the instance generics, or any top-level generics would be controlled by your synthesis script, i.e., from Tcl code.
I'll show you how, just post a couple of examples of how you want your code to be used.
Cheers,
Dave
Honored Contributor
