RAM uninferred due to asynchronous read logic

Yes, I have seen this exact circumstance - a register for the output of one RAM is the address register for another. QII synthesis makes an early decision of which register to pull in to each RAM to make it synchronous. Unfortunately, this is done independently for each RAM, so there's nothing to prevent the tool from choosing the same register for each RAM which then results in one RAM or the other not being inferred correctly. Does the second RAM have output registers in the RTL? I believe QII prefers to use the output register if available to make the RAM synchronous, so if you add the output register, it may stop the tool from trying to choose the read address register (which is the same as the output register already being chosen by the first RAM).