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Altera_Forum's avatar
Altera_Forum
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15 years ago

RAM uninferred due to asynchronous read logic

Hello, I have a cache module which uses an inferred synchronous RAM block. When I synthesize the module by itself (as the project's top module) the synthesis works as intended and the RAM is in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

In Quartus, from the Assignments menu, select "Design Partitions Window". Then from the Project Navigator window find all instances of your RAM and either right click to create a partition around it or click and drag it to the Design Partitions Window. If the code infers into memory when compiled at the top level, then I am pretty sure this will do the trick.