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Altera_Forum
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15 years ago

RAM uninferred due to asynchronous read logic

Hello, I have a cache module which uses an inferred synchronous RAM block. When I synthesize the module by itself (as the project's top module) the synthesis works as intended and the RAM is in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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In my original code (the code that failed) the uninferred RAM data output was connected straight to the address input of a different RAM block. Can this be the source of the trouble?

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Yes, that's sounds plaubsible. I guess, it's a somewhat unusual connection, so it most likely hasn't been considered by Altera.

The reported behaviour of not inferring a RAM although the conditions are apparently met seems like a bug to me. You should also tell to Altera support.